1. Field of the Invention
The present invention relates to a method of patterning a resist during a lithography process in manufacturing a semiconductor device. Particularly, the invention relates to a patterning method employing a silylating process.
2. Description of the Prior Art
Recent semiconductor technologies have improved the speed and integration of semiconductor devices and elements. This has increased the necessity of minimizing patterns formed on the semiconductor devices and of improving accuracy of the patterns.
A prevalent lithography process employs a photosensitive polymer (resist) pattern as a mask to etch a base thin film according to a reactive ion etching (RIE) method. The resist pattern shall be formed accurately with high aspect ratio on the stepped surface of a semiconductor element. This requirement is hardly met with a monolayer process of optical lithography technique. This increases the importance of employing a multilayer resist method.
According to the multilayer resist method, multiple layers provide respective resist functions. Namely, a resist layer of 2 to 3 .mu.m in thickness is disposed on the surface of a semiconductor element to flatten steps formed on the surface of the element and absorb light reflected by a substrate of the element. On the resist layer, a high-resolution resist layer is disposed to form a pattern. Since the exposure and development of the pattern is carried out away from the substrate and under ideal conditions, the pattern will be of high resolution and have accurate dimensions.
The multilayer resist method is achieved in various ways depending on the number of layers and the techniques of transferring a pattern to lower layers.
A typical one of the multilayer methods is a three layer resist method which provides upper and lower resist layers and an intermediate resist layer disposed between the upper and lower resist layers. According to the three layer resist method, a pattern is transferred from the upper layer to the intermediate layer and from the intermediate layer to the lower layer with the use of a reactive ion etching (RIE) process. The intermediate layer prevents the upper and lower resist layers from interacting with each other and provides pressure resistance for the lower resist layer when the lower layer is subjected to the RIE process. To achieve this function, the intermediate layer is usually made of SOG (spin on glass, i.e., organic silicon glass) formed according to a spin coating method.
The three layer resist method is relatively stable compared to other methods. However, it involves complicated processes, including two RIE processes, so that the three layer resist method may not be practical to apply for mass production.
To simplify the processes, various techniques have been discussed. One of the more promising techniques is a silylating process. This process realizes the function of the three layer resist method, but only with monolayer resist. Therefore, the silylating process may be an ideal and ultimate resist process.
A Japanese Laid Open Patent Application No. 61-107346 discloses a typical silylating process. This process will be explained with reference to FIGS. 1(a) to 1(d).
In FIG. 1(a), the surface of a substrate 1 is coated with a photosensitive resin layer 2, and a mask 3 is disposed on the resin layer 2. The resin layer 2 with the mask 3 on it is exposed against exposure rays 4 such as ultraviolet rays to form exposed portions 5 on the photosensitive resin layer 2, as shown in FIG. 1(b). Silicon compounds are applied to the exposed portions 5. The silicon compounds are selectively absorbed by the exposed portions 5 to form silylated layers 6 as shown in FIG. 1(c). Then, an etching process is carried out to remove non-exposed portions of the photosensitive resin layer 2 to form a pattern as shown in FIG. 1(d).
According to such a conventional silylating process, not only the exposed portions 5 but also the non-exposed portions are silylated to form silylated layers 6a. The layers 6a are minor if compared to the silylated layers 6, but the layers 6a deteriorate selectivity of the pattern. Therefore, the conventional silylating process is not practically applicable and, depending on conditions, it causes cracks as shown in FIG. 2.
The silylated layers 6a formed on the non-exposed portions, respectively, shall be removed. For this purpose, mixed gases such as gases of CF.sub.4 and O.sub.2 or gases of C.sub.2 F.sub.6 and O.sub.2 are used to etch the silylated layers 6a. However, when the silylated layers 6a on the non-exposed portions are etched with the mixed gases, the silylated layers 6 on the exposed portions are also etched. Since an etching speed of the exposed portions is higher than that of the non-exposed portions, the silylated layers 6 are etched more than the silylated layers 6a. Then, the pattern is not accurately formed. In addition, the reactive etching with oxygen may leave scum.